Cascaded H-Bridge Multilevel Inverter (Five-Level)

Most small inverters output a two-level square-ish waveform: cheap to build, but rich in harmonics that heat up motors, buzz in audio equipment and distort measurements. Multilevel inverters solve this by stacking smaller voltage steps into a staircase that approximates a sine wave, cutting harmonic distortion and switching stress. The cascaded H-bridge is the textbook topology for the idea — series-connected H-bridge cells, each fed by its own isolated DC source, whose outputs add up step by step. This project builds a single-phase five-level version as a low-voltage lab prototype: two MOSFET H-bridge modules, two isolated 12 V DC supplies, opto-isolated gate drivers and an Arduino generating the switching sequence. A CRO probe point lets the five-step staircase be captured and compared against a two-level waveform. It is a teaching prototype for power-electronics concepts — topology, isolation, dead time and harmonic content — not a mains appliance.

1. Two isolated 12 V DC supplies power the two H-bridge modules independently.
2. The Arduino computes gate timing from its switching-angle table and outputs eight logic signals.
3. Opto-isolated drivers translate these into gate drive for the eight MOSFETs, with dead time between complementary switches.
4. Each bridge contributes plus Vdc, zero or minus Vdc; the series connection sums them into the five-level staircase.
5. The staircase feeds a resistive demo load (lamp); an optional LC filter smooths it toward a sine.
6. CRO test points let the waveform be captured so the step levels can be observed and compared against two-level output.

Tech stack:

• Power MOSFETs on aluminium heatsinks (two H-bridge modules)
• Opto-isolated gate driver ICs
• Arduino Uno/Nano (switching sequence generation)
• Two isolated 12 V transformer-rectifier DC supplies
• DC-link electrolytic capacitors
• Resistive demo load (lamp) with optional LC filter
• CRO/DSO for waveform verification

• [Two cascaded H-bridge modules] Eight power MOSFETs on heatsinks form two full bridges whose outputs add in series to synthesise the five-level staircase.
• [Isolated DC sources] Two separate transformer-rectifier 12 V supplies give each bridge its own floating DC bus — the key isolation requirement of the topology, demonstrated physically.
• [Opto-isolated gate drivers] Driver ICs isolate the Arduino's 5 V logic from the power stage, a standard power-electronics safety practice.
• [Arduino switching sequence] The Arduino generates the eight gate signals with programmed dead time; the switching-angle table is editable in firmware.
• [Five-level staircase output] Plus 2Vdc, plus Vdc, zero, minus Vdc and minus 2Vdc steps at 50 Hz fundamental, captured at the CRO test point.
• [Fuse and snubber protection] Each DC bus is fused; gate resistors and freewheeling paths are documented in the wiring guide.
• [Buyer-run waveform comparison] The demo script compares the five-level output against a two-level bridge waveform on the same CRO to show the harmonic improvement.
• [Configurable switching angles] Angles can be edited to observe their effect on the step shape — a hands-on selective-harmonic-elimination concept demo.

• Assembled five-level inverter prototype
• Arduino firmware with switching-angle table
• Wiring and power-stage diagram
• Component list
• Project report PDF (topology, switching scheme, waveform analysis)
• PPT presentation for final review
• Viva Q&A preparation document (multilevel topologies, harmonics, gate driving, isolation)
• CRO demo and comparison script

• Low-voltage lab prototype: it is not a mains inverter and must never be connected to the 230 V grid.
• THD figures are not pre-claimed; harmonic content is observed by the buyer on a CRO or analyser during the demo.
• Resistive demo load only — inductive motor loads need the output filter and sit outside the base scope.
• Two isolated supplies add cost and weight; that trade-off is discussed in the report rather than hidden.
• Dead time and driver delays limit the usable switching frequency; the report documents the chosen values.