In this guide
Ask an experienced engineer to name the single component that fixes the most student circuit problems, and many will say the same thing: the 100nF ceramic capacitor sitting next to every IC's power pin. Microcontrollers that reset randomly, sensors with noisy readings, radios that drop connections when the processor wakes up — an astonishing fraction of these trace back to missing, misplaced, or misunderstood decoupling capacitors.
This guide explains why ICs need local charge reservoirs, what each capacitor in the decoupling network does, exactly where to place them, which types to use, and the layout mistakes that neutralize them.
Why: the current spike problem
When a digital IC switches — a clock edge, an output changing state, the ESP32's WiFi radio firing up — it demands a sharp pulse of current right now, on nanosecond timescales. The power supply is centimetres away, connected through PCB traces that have inductance. Inductance resists sudden current changes (V = L·di/dt), so the supply cannot deliver the pulse in time. The IC's supply voltage momentarily sags — and if it sags below the brownout threshold, the MCU resets; if it sags partially, analog readings wobble and timing glitches.
A decoupling capacitor is a local energy reservoir sitting millimetres from the IC: it supplies the fast current pulse instantly, then recharges slowly from the main supply between pulses. It also works in reverse — it shunts the IC's switching noise to ground instead of letting it pollute the shared power rail.
Two numbers make this concrete. The ESP32 can draw ~250mA peaks during WiFi transmit, switching in nanoseconds. And a 10cm PCB trace has roughly 60–100nH of inductance — at a 10ns current edge, even 100mA through 100nH drops L·di/dt = 1V. That's the physics your capacitors are fighting.
The decoupling network: each capacitor's job
A proper decoupling network has (at least) two tiers:
| Capacitor | Typical value | Job | Placement |
|---|---|---|---|
| High-frequency ceramic | 100nF (0.1µF) X7R MLCC | Supplies fast switching transients | Within 2–3mm of each power pin |
| Bulk | 10–47µF (MCU), 100–470µF (motor drivers, radios) | Supplies slower, larger current pulses; steadies the rail | Near the IC or at the power entry of the section |
Why two? Every real capacitor is only capacitive up to its self-resonant frequency — above that, its own parasitic inductance dominates and it behaves like an inductor. A 100nF ceramic in an 0603 package stays capacitive into the hundreds of MHz; a 100µF electrolytic gives up in the low MHz. The small cap handles the fast edges, the big cap handles the bulk energy. One cannot do the other's job.
Some designs add a middle tier (1µF) for good measure. Diminishing returns set in quickly — correct placement of the two tiers beats a scatter of extra values placed poorly.
Placement: millimetres matter more than microfarads
This is the part most students get wrong. A 100nF capacitor placed 3cm away through thin traces has so much trace inductance in series that it's nearly useless at the frequencies that matter. The rules:
- One 100nF per power pin (per VDD/VSS pair on chips with multiple supply pins — ESP32, STM32). Not one per chip. Per pin.
- Closest possible to the pin — within 2–3mm, capacitor body nearly touching the IC.
- Short, wide traces from the capacitor to the power pin and to ground. Every millimetre of thin trace adds inductance.
- Via directly to the ground plane from the capacitor's ground pad — don't route the ground connection on a long trace to some distant ground point.
- Power pin → capacitor → via should be the current path, in that order. The capacitor sits between the pin and the rest of the board.
- Bulk capacitor nearby — within a centimetre or two of the IC, at the section's power entry.
On a two-layer board with a solid ground pour, this means: 100nF tucked against each supply pin, ground pad via'd straight down to the pour. On perfboard or breadboard prototypes, push the capacitor's leads as close to the IC pins as physically possible — lead inductance counts too.
Note: The capacitor value matters less than the placement. A 100nF cap 2mm from the pin outperforms a 1µF cap 30mm away at the frequencies where decoupling actually works. When a circuit misbehaves, check placement before changing values.
Choosing the capacitor type
| Type | Strengths | Weaknesses | Use for |
|---|---|---|---|
| MLCC ceramic (X7R) | Tiny, cheap, excellent high-frequency behavior | Capacitance drops with DC bias and temperature (derate!) | The 100nF high-frequency tier |
| MLCC ceramic (C0G/NP0) | Extremely stable | Only available in small values | Timing, filters — not decoupling |
| Tantalum | High capacitance in small size | Fails short if abused; needs voltage derating (50%) | Bulk where space is tight |
| Aluminium electrolytic | Cheap bulk capacitance | High ESR, dries out with age/heat | Bulk tier, power entry |
The X7R derating trap: a "100nF" X7R MLCC at 3.3V DC bias in a small package may actually be 60–70nF. It still works fine for decoupling (the circuit isn't precision-tuned), but don't assume marked value = effective value in precision applications. For the 100nF-per-pin job, standard X7R 0603/0805 ceramics are exactly right.
Voltage rating: use capacitors rated at least 2× the rail voltage (10V+ caps on a 3.3V rail, 16–25V on a 5V rail). This also reduces the DC-bias derating effect.
Decoupling in specific situations
ESP32 / WiFi MCUs: one 100nF per VDD pin plus a 10–47µF bulk nearby. The WiFi transmit bursts (~250mA peaks) will brownout-reset the chip without the bulk cap. If your ESP32 resets when WiFi connects, inadequate decoupling is suspect #1.
Motor drivers: 100nF at the logic supply pin plus 100–470µF bulk at the motor supply pins. Motor brush noise is brutal — the bulk cap absorbs the commutation spikes locally instead of broadcasting them down the rail (see EMI/EMC basics).
Analog sections: the ADC's Vref/AVDD pin gets its own 100nF + 1–10µF, ideally fed through a small ferrite bead or 10Ω resistor from the digital rail — an RC/LC filter that keeps digital switching noise out of the analog supply. (More in the ADC accuracy guide.)
Switching regulators: follow the datasheet layout exactly — input cap placement is part of the regulator's stability design, not a suggestion. The input ceramic must sit at the IC's input pins with minimal loop area.
Debugging with decoupling in mind
Symptoms that point at decoupling:
- MCU resets when a load switches on (WiFi, motor, relay) → bulk capacitance or placement
- Sensor readings get noisier when the processor is busy → shared rail noise, missing local caps
- Circuit works on the bench supply but fails on battery → supply impedance higher, decoupling matters more
- Touching the board changes the behavior → marginal stability, often supply-related
- Works at room temperature, fails hot or cold → capacitor derating or marginal timing meeting marginal supply
Quick experiments: clip a 100nF ceramic directly across the suspect IC's supply pins (dead-bug style, shortest leads possible). If the problem improves, the layout's decoupling is inadequate — fix the placement properly. Scope the rail AC-coupled with a short ground spring while the load switches: dips and ringing show you exactly what the capacitors aren't catching. (Probing technique in the oscilloscope guide.)
Common mistakes
- One capacitor for the whole board. Decoupling is per-pin, not per-board.
- Capacitor placed centimetres away "because it fit better there." Inductance doesn't care about your layout aesthetics.
- Ground routed on a long trace instead of via'd to the plane — the ground path inductance counts exactly like the power path.
- Only bulk, no ceramics (or vice versa). The tiers do different jobs.
- Sharing one 100nF between two ICs. Each pin pair gets its own.
- Forgetting the analog supply pin. The AVDD/Vref pin needs decoupling as much as the digital pins — often more.
- Upgrading values instead of fixing placement. A bigger capacitor farther away is not a fix.
Quick checklist
- 100nF X7R ceramic within 2–3mm of every IC power pin
- Ground pad via'd directly to the ground plane (short, wide traces)
- Bulk capacitor (10–470µF by application) at each section's power entry
- Analog supply separately decoupled, ideally LC/RC-filtered from digital rail
- Capacitor voltage ratings ≥2× rail voltage
- Switching regulator input caps per the datasheet layout example
Where to go from here
- PCB Layout: 10 Rules That Prevent Failures — decoupling is rule #2; the full layout checklist.
- EMI/EMC Basics for Student PCBs — why decoupling is also an emissions fix.
- ADC Resolution vs Accuracy — clean rails as the foundation of accurate measurement.
- How Crystal Oscillators Work — the other per-pin passive that demands correct placement.
- More electronics fundamentals in the Electronics / E&TC branch hub.